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| INTEGRATED CIRCUITS DATA SHEET TDA9888TS; TDA9889TS DVB selective AGC amplifier Product specification Supersedes data of 2002 Oct 23 2004 Nov 02 Philips Semiconductors Product specification DVB selective AGC amplifier FEATURES * Applicable for terrestrial and cable TV reception * 70 dB variable gain wide-band Intermediate Frequency (IF) amplifier (AC-coupled) * Gain control via external control voltage (0 to 3 V) * 2 V (p-p) differential low IF (downconverted) output for direct Analog-to-Digital Converter (ADC) interfacing * Digital Video Broadcast (DVB) downconversion with integrated selectivity (allows to use one SAW filter applications) * Integrated anti-aliasing tracking low-pass filter * Fully integrated synthesizer controlled oscillator with excellent phase noise performance * Synthesizer frequencies for a wide range of world wide DVB standards (for IF centre frequencies of 36, 44 and 57 MHz) with different channel bandwidths (6, 7 and 8 MHz) are possible; see Tables 1 and 2 * 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as crystal oscillator ORDERING INFORMATION TYPE NUMBER TDA9888TS TDA9889TS PACKAGE NAME SSOP16 DESCRIPTION TDA9888TS; TDA9889TS * Tuner Automatic Gain Control (TAGC) detector for independent tuner gain control loop applications * TAGC operating as peak-sync detector, fast reaction time due to additional speed-up detector * TAGC switch for feed-through of TAGC signal from analog TV demodulator (e.g. TDA9886) in case of hybrid (analog and digital TV demodulation) application * Stabilizer circuit for ripple rejection and to achieve constant output signals * Electrostatic discharge (ESD) protection for all pins. GENERAL DESCRIPTION The TDA9888TS; TDA9889TS is an AGC amplifier circuit with integrated selectivity. The device provides downconversion and filtering without alignment for all DVB standards. The filtering considers the tough neighbouring channel conditions. VERSION SOT338-1 plastic shrink small outline package; 16 leads; body width 5.3 mm 2004 Nov 02 2 Philips Semiconductors Product specification DVB selective AGC amplifier QUICK REFERENCE DATA SYMBOL VP IP Vo(LIF)(p-p) GIF(max) GIF(cr) fosc PARAMETER supply voltage supply current typical low IF operating output voltage (peak-to-peak value) maximum conversion gain IF gain control range synthesizer controlled oscillator frequencies note 1 CONDITIONS TDA9888TS; TDA9889TS MIN. 4.5 46 - TYP. 5 55 2 90 70 31 31.5 32 40 53 99 97 102 - - - MAX. 5.5 64 - - - - - - - - - - - +0.9 - - UNIT V mA V dB dB MHz MHz MHz MHz MHz dBc dBc dBc dB dB dB output peak-to-peak level to 85 input RMS level ratio see Fig.3 see Tables 1 and 2 60 - - - - - N(synth) synthesizer phase noise performance at 1 kHz at 10 kHz at 100 kHz 89 89 98 -0.9 15 30 LIF N-1 N+1 low IF band amplitude characteristic 0 dB at middle of band (standard independent) low-pass filter attenuation suppression of IF input frequencies below wanted band at low IF output carrier-to-noise ratio at low IF power supply ripple rejection [residual ripple AM, modulation factor m at 2 V (p-p) low IF signal] 8 MHz band; at 15.75 MHz input frequency between 21 and 31 MHz; referenced to 36 MHz at f > 1 MHz; see Fig.5 fripple = 70 Hz; see Fig.7 C/N PSRR 112 - 116 1.4 - - dBc/Hz % Note 1. Some parameters can be decreased at VP = 4.5 V. 2004 Nov 02 3 Philips Semiconductors Product specification DVB selective AGC amplifier BLOCK DIAGRAM TDA9888TS; TDA9889TS handbook, full pagewidth IF gain control input TAGC TADJ TAGCEXT 10 9 11 TUNER AGC AGC 6 S0 1 S1 13 S2 3 IF AGC INTERFACE TDA9888TS TDA9889TS LOGIC CONTROL IF1 IF2 15 16 DOWNCONVERTER AND COMPLEX FILTERING 8 LIF2 TRACKING LOW-PASS FILTER 7 LIF1 low IF output 2 V(p-p) differential SUPPLY SYNTHESIZER AND REFERENCE GENERATION 14 GND 4 LFS 2 REF FILTER REFERENCE CONTROL 5 LFLP 12 VP MHC094 4 MHz crystal or external reference Fig.1 Block diagram. 2004 Nov 02 4 Philips Semiconductors Product specification DVB selective AGC amplifier PINNING SYMBOL PIN S0 REF S2 LFS LFLP AGC LIF1 LIF2 TADJ TAGC TAGCEXT VP S1 GND IF1 IF2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION logic switch S0 input (frequency select) 4 MHz crystal or reference input logic switch S2 input (AGC select) loop filter synthesizer PLL loop filter low-pass control PLL AGC control voltage input low IF differential output 1 low IF differential output 2 tuner AGC TakeOver Point (TOP) adjustment tuner AGC output external tuner AGC voltage input supply voltage (+5 V) logic switch S1 input (frequency select) ground supply IF differential input 1 IF differential input 2 Tuner AGC handbook, halfpage TDA9888TS; TDA9889TS S0 REF S2 LFS 1 2 3 4 16 IF2 15 IF1 14 GND 13 S1 TDA9888TS LFLP 5 TDA9889TS 12 VP AGC LIF1 LIF2 6 7 8 MHC093 11 TAGCEXT 10 TAGC 9 TADJ Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION Figure 1 shows the simplified block diagram of the device. The integrated circuit contains the following functional blocks: 1. Gain controlled IF amplifier 2. Tuner AGC 3. Reference generation 4. Synthesizer for downconversion 5. Downconversion and complex filtering 6. Tracking low-pass filter with reference control 7. Low IF differential output stage 8. Logic control 9. Internal voltage stabilizer. Gain controlled IF amplifier The IF amplifier consists of three AC-coupled differential stages. Gain control is performed by emitter degeneration. Total gain control range is 70 dB (typ.). The differential input impedance is typical 2 k in parallel with 3 pF. The tuner AGC is realized by a TakeOver Point (TOP) network and a peak-level detector. The threshold level of the peak detector can be adjusted by an external potentiometer connected to pin TADJ. For IF signals above this threshold the level detector provides a discharge current to pin TAGC. An additional current source is internally connected to this pin providing charge current to the external tuner AGC capacitor. For IF signals of 8 dB below the threshold voltage this current will be increased by a factor of approximately 40 for faster AGC reaction. The ratio of discharge to charge current is normally approximately 2000 and approximately 50 for fast mode. For use of the device in different applications the charge current can be switched off, for hybrid applications the signal at pin TAGCEXT can be fed via a transmission gate to pin TAGC (TDA9888TS; TDA9889TS combined with analog IF), controlled by the 3-state input pin S2. With an activated transmission gate all internal currents are off. In the event that the tuner AGC is not needed (e.g. TAGC from channel decoder or from an analog IF in hybrid chassis), pin TADJ should be left open-circuit and therefore all internal AGC currents will be switched off. 2004 Nov 02 5 Philips Semiconductors Product specification DVB selective AGC amplifier Reference generation The 4 MHz crystal is the reference for the downconversion synthesizer and the filter synthesizer. The downconverted DVB frequency and the frequency adjustment of the integrated filters are dependent on the precision of the reference signal at pin REF. An operation as crystal oscillator is possible as well as connecting this input via a serial capacitor to another low-ohmic reference frequency source. The integrated divider-by-8 generates the internally needed 500 kHz reference frequency for the DVB synthesizer and the reference filter. Synthesizer for downconversion The PLL synthesizer for downconversion consists of a Voltage Controlled Oscillator (VCO), a divider with a standard dependent divider factor, a frequency phase detector (constructed as a digital 3-state comparator) and a charge pump. The VCO operates as an integrated low radiation relaxation oscillator at double the conversion frequency. For downconversion the VCO frequency is divided-by-2 to provide two differential square wave signals with exactly 90 degrees phase difference, independent of the VCO frequency. The frequency phase detector compares the down-divided oscillator signal with the 500 kHz reference frequency signal and controls, via the charge pump, the control voltage at the external loop filter connected to pin LFS, which is required to tune the VCO exactly to the wanted frequency. The divider, the frequency phase detector and the reference frequency divider are constructed in a low radiation technique to optimize the synthesizer spurious suppression in the downconverted output signal. Downconversion and complex filtering The gain controlled IF signal from the IF amplifier is fed to two identical linear mixers, operating in the `in phase' and `quadrature' mode in accordance to the 0 and 90 degree VCO signal from the synthesizer. With this, the downconverted DVB low IF signal is available as an I and Q signal in the frequency band from 1 to 9 MHz. These signals are fed to the complex filter section. As a result of adding both signals, the unwanted mirror signal will be attenuated (approximately 34 dB). The unwanted frequency components below 1 MHz are attenuated in a high-pass filter. This signal is then fed through a group-delay equalizer circuit. 2004 Nov 02 6 TDA9888TS; TDA9889TS Tracking low-pass filter with reference control The low-pass filter is controlled by a reference signal [generated by a frequency synthesizer and can be switched by the standard selection (S0 and S1)]. The tracking low-pass filter is designed as a Tschebyscheff filter to guarantee sufficient suppression for the neighbouring picture carrier. An all-pass filter corrects the characteristic to obtain a flat (equivalent ripple) group delay behaviour. Low IF differential output stage The output amplifier consists of two identical differential operational amplifiers with a high common mode (DC) rejection ratio, to provide a constant DC voltage at the output stage. The amplified Low IF (LIF) signal is available as a differential signal with an amplitude of 2 V (p-p) and DC level of 2 V (typ.) between the output terminals of both amplifiers. Logic control The logic control provides an easy selection of the most common standards for Europe, USA and Japan with the two switches S0 and S1 (frequency selection different for TDA9888TS and TDA9889TS) and controls all internal standard dependent stages. The five available tuner AGC modes can be set via the 3-state input pin S2 and RTOP connection (at pin TADJ). Internal voltage stabilizer The band gap circuit generates a voltage of approximately 2.4 V, independent of the supply voltage and the temperature. A voltage regulator circuit, controlled by this voltage, produces a constant voltage of 3.55 V which is used as an internal reference voltage. Philips Semiconductors Product specification DVB selective AGC amplifier LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VP supply voltage PARAMETER TDA9888TS; TDA9889TS CONDITIONS IP = 64 mA; Tamb = 70 C; maximum chip temperature of 125 C; Rth(j-a) = maximum - MIN. MAX. 5.5 UNIT V Vi(n) tsc Tstg Tamb Ves input voltage at pins 1 to 11, 13, 15 and 16 short-circuit time to ground or VP storage temperature ambient temperature electrostatic handling voltage for all pins note 1 note 2 - - -25 -20 -200 -2500 VP 10 +150 +70 +200 +2500 V s C C V V Notes 1. Machine model (class B; SNW-FQ-302B): discharging a 200 pF capacitor via a 0.75 H inductance. 2. Human body model (class 2; SNW-FQ-302A): discharging a 100 pF capacitor via a 1.5 k series resistor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 136 UNIT K/W 2004 Nov 02 7 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS CHARACTERISTICS VP = 5 V; Tamb = 25 C; 8 MHz system; see Tables 1 or 2, CW test input signal is used for specification; Vi(IF)(rms) = 10 mV frequency fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to low IF differential output of 2 V (p-p); measurements taken in test circuit of Fig.11 with external 4 MHz reference signal of 140 mV (RMS); unless otherwise specified. SYMBOL Supply; pin VP VP IP Ptot GIF(max) GIF(min) GIF(cr) BIF(-3dB)(ll) BIF(-3dB)(ul) Ri(dif) Ci(dif) VI Vo(LIF)(p-p) Vclip(u) Vclip(l) Ro(diff) VO Ibias(int) supply voltage supply current total power dissipation note 1 4.5 46 - output peak-to-peak level to input RMS level ratio see Fig.3 note 2 note 2 note 2 note 2 85 - 60 - - - - - - 2.9 - note 2 - - 0.8 2.5 note 3 note 2 0 dB at middle of band (standard independent) from 1 MHz to 2 MHz from 2 MHz to end of band N-1 low-pass filter attenuation 6 MHz band; at 11.75 MHz 7 MHz band; at 13.75 MHz 8 MHz band; at 15.75 MHz 27MHz 2004 Nov 02 low-pass filter attenuation any band; at 27 MHz 8 0.6 1.7 -0.9 - - 15 15 15 40 5 55 275 5.5 64 352 - 23 - - - - - - - - 0.6 150 - - - - - +0.9 150 100 - - - - V mA mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IF amplifier; pins IF1 and IF2; differential maximum conversion gain minimum conversion gain IF gain control range lower limit -3 dB IF bandwidth upper limit -3 dB IF bandwidth differential input resistance differential input capacitance DC input voltage 90 20 70 15 80 2 3 1.9 dB dB dB MHz MHz k pF V Low IF output signal; pins LIF1 and LIF2; differential; see Fig.8 typical low IF operating output voltage (peak-to-peak value) upper clipping voltage level (single-ended) lower clipping voltage level (single-ended) output resistance (differential) DC output voltage internal DC bias current for emitter-follower (single-ended) 2 - - - 2 1 - - - - - - - - - 50 V V V V mA mA mA k dB ns ns dB dB dB dB Io(source)(max) maximum AC and DC output source current (single-ended) Io(sink)(max) ZL(diff) LIF td(g)(LIF) maximum AC and DC output sink current (single-ended) differential load impedance low IF band amplitude characteristic low IF band group delay ripple Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS SYMBOL N+1 PARAMETER suppression of IF input frequencies below wanted band at low IF output carrier-to-noise ratio at low IF CONDITIONS input frequency between 21 and 31 MHz; referenced to 36 MHz at f = 4.9 MHz; note 4a; see Fig.5 at f = 4.9 MHz; note 4b; see Fig.5 MIN. 30 TYP. 35 - MAX. UNIT dB C/N 112 90 35 116 100 - - - - dBc/Hz dBc/Hz dB d3 intermodulation at fLIF1 = 4.1 MHz or fLIF2 = 5.9 MHz in-band harmonics low IF = multiple of 1.31 MHz up to 7.86 MHz in-band spurious elements (1 to 9 MHz) out-band spurious elements (>9 MHz) fIF1 = fosc + 4.7 MHz and fIF2 = fosc + 5.3 MHz; see Fig.6 fIF1 = fosc + 1.31 MHz d2 40 - - dB H(spur) AC load: ZL(diff) > 1.7 k 50 50 - - - 25 1400 2700 1.4 - - 5 35 2000 4000 - dB dB Hz Hz Hz Hz % PSRR power supply ripple rejection [residual ripple FM, peak deviation f at 2 V (p-p) low IF signal] fripple = 70 Hz; see Fig.7 fripple = 1 kHz; see Fig.7 fripple = 10 kHz; see Fig.7 fripple = 100 kHz; see Fig.7 - - - - - power supply ripple rejection fripple = 70 Hz; see Fig.7 [residual ripple AM, modulation factor m at 2 V (p-p) low IF signal] IF AGC control; pin AGC Ii(sink)(max) Vi(max) Gv SAGC maximum input sink current maximum allowable input voltage gain control voltage range negative control steepness GIF/Vcon Gv = 0.8 to 2.2 V - - 0 - - - - 45 2 VP 3 - A V V dB/V Tuner AGC; pin TAGC, operating as current output; see Figs 3 and 4 Vi(IF)(min)(p-p) minimum controlled IF input signal voltage between pins IF1 and IF2 (peak-to-peak value) Vi(IF)(max)(p-p) maximum controlled IF input signal voltage between pins IF1 and IF2 (peak-to-peak value) Vi(IF)/T Isink variation of AGC controlled IF input voltage with temperature sink current (tuner AGC discharge current) RTOP = 22 k; ITAGC(sink) = 100 A - 81 84 dBV RTOP = 0 ; ITAGC(sink) = 100 A 102 106 - dBV RTOP = 8.2 k; ITAGC(sink) = 100 A VTAGC = 1 V - 400 - 500 0.07 600 dB/K A 2004 Nov 02 9 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS SYMBOL Isource(1) Isource(2) Vsat(ul) Vsat(ll) TH PARAMETER source current (tuner AGC charge current) upper limit saturation voltage lower limit saturation voltage level loss threshold of internal detector for activating fast AGC fast AGC detection off time CONDITIONS normal mode fast mode activated by internal level detector pin operating as current output 0 dB corresponds to RTOP alignment all signal events below TH 8 MIN. 0.21 TYP. 0.27 10 MAX. 0.33 12 - 0.3 10 UNIT A A V V dB VP - 0.3 - - 6 - 8 tdet(off) Ron Vop(I/O) VRTOP VTADJ RTOP 40 - 0 60 80 ms V External tuner AGC; electronic switch operation; pin TAGC connected to pin TAGCEXT resistance between pins TAGC and TAGCEXT in operation I/O operating voltage range 900 - - 3.5 - - - 4 9 4.7 - 1200 VP 2 - 25 - 3 - - 5.65 65 Tuner AGC takeover point adjust and TAGC operating mode settings; pin TADJ; see Table 3 alignment voltage voltage at pin TADJ resistor connected between pin TADJ and GND RTOP at pin TADJ = 0 to 22 k pin open-circuit for LOW: RTOP at pin TADJ for HIGH: pin open-circuit 0 - - 1 V V k M Low-pass control PLL; pin LFLP VLFLP KO KD Rlf(int) Isink/source loop filter operating range VCO steepness: fVCO/VLFS phase frequency detector steepness: ILFLP/FM internal loop filter resistor phase frequency detector I/O current note 5 1 - - 3.75 - V MHz/V A/rad k A Synthesizer PLL; pin LFS VLFS KO KD Isink/source N(synth) loop filter operating range VCO steepness: fVCO/VLFS phase frequency detector steepness: ILFS/FM phase frequency detector I/O current synthesizer phase noise performance at 1 kHz at 10 kHz at 100 kHz at 1.4 MHz spur Ileak(lf) synthesizer spurious performance loop filter leakage current multiple of f = 500 kHz synthesizer spurious performance > 50 dBc 10 note 5 1 - - - 89 89 98 115 50 - - 25 16 - 99 97 102 119 - - 3 - - 100 - - - - - 10 V MHz/V A/rad A dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc nA 2004 Nov 02 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS SYMBOL PARAMETER CONDITIONS MIN. - - TYP. MAX. UNIT Standard switch S0 and S1; pins S0 and S1; see Tables 1 or 2 Vi Vfr(S0,S1) Ri Vi input voltage free-running voltage at pin S0 or pin S1 input resistance for LOW for HIGH pin open-circuit; Ifr(S0,S1) < 0.1 A 0 2.5 - - for LOW for MID for HIGH Vfr(S2) Ri VI Ri Ci Rxtal Cx fref fref Vref(p-p) Ro(ref) CK free-running voltage at pin S2 input resistance pin open-circuit; Ifr(S2) < 0.1 A 0 1.3 2.5 - - 2.3 1.5 - note 7 note 8 operation as input terminal 2 VP - - 0.8 2 VP - - 2.9 2.5 - 200 - 100 x 10-6 1100 4.7 - mV k pF V V V k 3.5 37 - - - 1.65 25 Standard switch S2; pin S2; see Table 3 input voltage V V V V k Reference input; pin REF; note 6 DC input voltage input resistance input capacitance pull-up/down capacitance frequency of reference signal tolerance of reference frequency amplitude of reference signal source (peak-to-peak value) allowed output resistance of external reference source decoupling capacitance to external reference source operation as input terminal 2.6 2 2 - 4 - - - 100 V k pF pF MHz resonance resistance of crystal operation as crystal oscillator - - - 230 - 22 depends on crystal type 2004 Nov 02 11 Philips Semiconductors Product specification DVB selective AGC amplifier Notes 1. Some parameters can be decreased at VP = 4.5 V. TDA9888TS; TDA9889TS 2. This parameter is not tested during production and is only given as application information. 3. For a higher AC load a resistor application is possible. 4. Measured without input signal but AGC adjusted corresponding to following input level a) 10 mV (RMS) b) 0.5 mV (RMS). 5. Calculation of the PLL loop filter by using following formulae, valid under the condition for the damping factor d 1.2 . KO 1 KO 1 BL -3 dB = ------ ------ D R LFS and d = -- R LFS ------ K D C LFS with the following parameters - -K 2 n n 2 KO = VCO steepness (rad/V) or (2 Hz/V), KD = phase frequency detector steepness (A/rad), RLFS = synthesizer loop filter serial resistor (), CLFS = synthesizer loop filter serial capacitor (F), BL-3dB = loop filter bandwidth at -3 dB amplitude (Hz), d = damping factor n = divider factor; see Table 4. 6. The reference input at pin S2 is able to operate as a one-pin crystal oscillator as well as an input terminal with external reference signal, e.g. from the tuning system. 7. The value of Cx determines the accuracy of the resonance frequency of the crystal and depends on the crystal type. 8. The tolerance of the reference frequency determines the accuracy of the low IF. The tolerance of fosc is given by f ref f osc = ---------- f osc and the tolerance of fLIF is given by fLIF = -fosc. f ref Table 1 Standard switch settings for TDA9889TS S1 HIGH HIGH LOW LOW S0 HIGH LOW HIGH LOW fIF(centre) (MHz) 36 36 44 36 fosc (MHz) 31 31.5 40 32 CHANNEL BANDWIDTH (MHz) 8 7 6 6 REGION Europe Europe USA Europe 2004 Nov 02 12 Philips Semiconductors Product specification DVB selective AGC amplifier Table 2 Standard switch settings for TDA9888TS S1 HIGH HIGH LOW LOW Table 3 S0 HIGH LOW HIGH LOW fIF(centre) (MHz) 36 36 44 57 fosc (MHz) 31 31.5 40 53 TDA9888TS; TDA9889TS CHANNEL BANDWIDTH (MHz) 8 7 6 6 REGION Europe Europe USA Japan AGC mode settings S2 RTOP connected FUNCTION (PIN TADJ) all currents off; voltage from pin TAGCEXT switched to pin TAGC charge currents disabled; discharge current enabled all charge and discharge currents enabled open-circuit all currents off; pin TAGC high-ohmic all currents off; voltage from pin TAGCEXT switched to pin TAGC LOW MID HIGH MID/HIGH LOW Table 4 Synthesizer PLL loop filter dimensions for different standards; see note 5 of Chapter "Characteristics" fosc (MHz) 31 31.5 32 44 57 40 53 n 62 63 64 80 106 BL-3dB (kHz) 36.1 35.6 35 34 34.4 d 1.22 1.21 1.20 1.31 1.52 6.8 9.1 18 15 RLFS (k) 5.6 CLFS (nF) 4.7 CP(LFS) (pF) 22 fIF(centre) (MHz) 36 2004 Nov 02 13 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS MHC095 handbook, halfpage V TAGC (V) 3 ITAGC (A) 600 500 400 handbook, halfpage 120 Vi(IF)(rms) (dBV) 100 MHC096 2 300 200 1 (1) (2) (3) (4) 90 80 100 0 70 0 40 60 80 120 Vi(IF)(p-p) (dBV) 100 60 0 4 8 12 16 20 24 RTOP (k) (1) IF AGC voltage. (2) Ituner; RTOP = 22 k. (3) Ituner; RTOP = 8.2 k. (4) Ituner; RTOP = 0 . Fig.4 Fig.3 Typical IF and tuner AGC characteristic. Typical tuner takeover point as a function of RTOP. handbook, halfpage 1 V (p-p) 74 dBV MHC097 handbook, halfpage 120 C/N (dBc/Hz) 110 31.0 fosc 35.7 36.3 fIF input conditions (MHz) Intermodulation 100 handbook, halfpage MHC098 4.1 4.7 5.3 5.9 output signal fLIF (MHz) 90 80 30 50 70 90 110 Vi(IF)(rms) (dBV) 31.0 32.31 fIF fosc (MHz) input conditions 0 1.31 2.62 3.93 5.24 6.55 7.86 9.17 fLIF (MHz) output signal Harmonics MHC105 Fig.5 Typical C/N ratio as a function of IF input voltage. Fig.6 Intermodulation and harmonics. 2004 Nov 02 14 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS VLIF handbook, halfpage (dB) 1 handbook, halfpage 2 MHC100 td(g)(LIF) (ns) V = VP + Vripple MHC099 0 -1 (3) TDA9888TS TDA9889TS -2 -3 -4 -5 -6 -7 (1) (2) 200 150 100 50 0 -50 VP (V) 5.050 5.000 4.950 -8 -9 -10 0 2 4 6 8 10 12 -100 14 16 f (MHz) tolerance scheme: (1) (2) (3) t (s) (1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz. Fig.8 Fig.7 Ripple rejection condition. Detailed low IF amplitude and group delay pass band tolerance scheme. handbook, halfpage V 30 LIF (dB) 10 MHC101 handbook, halfpage V 30 LIF (dB) 10 -10 MHC102 -10 -30 -50 -30 -50 -70 -90 (3) (2) (1) -70 -90 -30 (3) (2) (1) -25 -20 -15 -10 -5 0 f (MHz) 0 5 10 15 20 25 30 f (MHz) (3) tolerance scheme: (1) (2) (3) tolerance scheme: (1) (2) (1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz. (1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz. Fig.9 Low IF amplitude stop band tolerance scheme. Fig.10 Low IF amplitude pass band tolerance scheme. 2004 Nov 02 15 Philips Semiconductors Product specification DVB selective AGC amplifier TEST AND APPLICATION INFORMATION TDA9888TS; TDA9889TS handbook, full pagewidth GND 51 H IF input 1:1 S1 IF input 16 15 14 13 L + VP TAGC external TAGC TADJ RTOP 22 k 10 nF 12 11 10 9 TDA9888TS TDA9889TS 1 S0 L H 10 nF Cx 4 MHz 2 fref 3 S2 L MH 10 nF + VP LFS LFLP AGC LIF1 LIF2 MHC103 4 5 6 7 8 CLFS 4.7 nF RLFS 5.6 k CLFLP 47 nF 100 pF 51 external reference input circuit REF Fig.11 Test circuit. 2004 Nov 02 16 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS handbook, full pagewidthtuner AGC 100 nF IF input 5 SAW FILTER 51 2 X7253D 4 3 1 GND + VP 10 nF TADJ RTOP 22 k (2) (2) IF input 16 15 14 13 12 11 10 9 TDA9888TS TDA9889TS 1 2 3 4 CP(LFS) 22 pF CLFS 4.7 nF RLFS 5.6 k REF + VP LFS LFLP CLFLP 47 nF 47 k(1) CHANNEL DECODER MHC104 5 6 100 nF(1) 7 8 Cx 4 MHz fIF = 36 MHz; channel bandwidth = 8 MHz; external AGC from channel decoder; inclusive narrow band tuner AGC. (1) Depends on channel decoder. (2) Open-pin if tuner AGC is not needed. Fig.12 Application circuit. 2004 Nov 02 17 Philips Semiconductors Product specification DVB selective AGC amplifier PACKAGE OUTLINE TDA9888TS; TDA9889TS SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2004 Nov 02 18 Philips Semiconductors Product specification DVB selective AGC amplifier SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. TDA9888TS; TDA9889TS To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C. 2004 Nov 02 19 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar soldering or manual soldering is suitable for PMFP packages. not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7) SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable not suitable 2004 Nov 02 20 Philips Semiconductors Product specification DVB selective AGC amplifier DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development TDA9888TS; TDA9889TS DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2004 Nov 02 21 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2004 SCA76 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R25/03/pp22 Date of release: 2004 Nov 02 Document order number: 9397 750 14249 |
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